TID/TNID and SEE environment; SEU, SET, SEL and MBU risk; radiation-hard, radiation-tolerant or characterized commercial device selection; TMR or hardened elements; EDAC/ECC; memory and configuration scrubbing.
VERTICAL-SPECIFIC SYSTEMS
Table stakes change with the mission.
A payload, medical imager, autonomous platform, radio, storage controller and emulation environment do not fail, or earn acceptance, in the same way. We align architecture and evidence to the applicable mission, safety, assurance and interoperability context.
01 · SPACE & MISSION SYSTEMS
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEPlanet Labs microsatellite imaging
Close payload behavior against radiation, recovery and mission life.
Sustained rate, memory margin, fault containment and command behavior must close as one payload path, not as independent RTL blocks.
Sensor→Acquire & calibrate→Buffer & compress→Secure→Frame & code→RF / ground
DOMAIN TABLE STAKES
Radiation and fault containment
Flight assurance
FDIR, watchdogs, safe states and reset domains; derating, thermal and mission-life margins; CDC/RDC and timing; fault injection, bidirectional traceability and independent review.
Program-selected assurance: ECSS where invoked · NASA/DoD/customer RHA and EEE-parts requirements as flowed down · DO-254 only when included in an airborne certification basis
- Acceptance evidence
- Rate and buffer margin, packet integrity, reset recovery and representative end-to-end payload tests
Stratix 10 RTL spanning Camera Link acquisition, PCIe transfer, AES image encryption, control peripherals and DVB-S2 communications, including pipeline repair and feature delivery.
02 · MEDICAL IMAGING
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEPhilips Healthcare IVUS imaging
Correlate acquisition, processing and transport.
The useful boundary spans acquisition timing, numerical behavior, control, optical or PCIe transport and host presentation.
Transducer / sensor→ADC & timing→FPGA DSP→Deterministic transport→Host image
DOMAIN TABLE STAKES
Patient risk and lifecycle
Signal integrity and safe operation
Hazard analysis, risk controls and control verification; intended use and essential performance; bidirectional requirements traceability, configuration control, anomaly handling and reproducible releases.
Calibration and acquisition integrity; bounded numerical error and latency; single-fault behavior, EMC immunity, secure update, SBOM and threat modeling for connected devices.
Applied where relevant to device scope: ISO 14971 · IEC 62304 · IEC 60601-1 and -1-2 · IEC 62366-1 human factors · ISO 13485 / FDA QMSR · FDA cybersecurity guidance
- Acceptance evidence
- MATLAB-to-RTL correlation, timing bounds, data integrity, deterministic fault behavior and target tests
Virtex-6 imaging RTL with ADC/DDR2 acquisition, catheter-motor control, Aurora/SFP+ transport and PCIe delivery to the display system. A separate stereo-vision FPGA platform was later licensed for surgical-robotics use.
03 · ROBOTICS, DRONES & AUTONOMY
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEAeva RFSoC LiDAR and Compound Eye stereo vision
Make sensing latency and recovery observable.
Partition synchronized acquisition, deterministic preprocessing, sensor fusion and control against measured latency, bandwidth, power and degraded behavior.
Synchronized sensors→Align & condition→Extract features→Sensor fusion→Control↺Scenario replay
DOMAIN TABLE STAKES
Safety architecture
Real-time integration
Operating-domain and hazard analysis; safety goals, FMEA or STPA; sensor health and disagreement; watchdogs, redundancy, emergency stop, degraded modes and deterministic fallback.
Timestamp lineage and synchronization; bounded latency and jitter; CAN/CAN-FD and Ethernet; ROS 2, RTOS or Linux where appropriate; SIL, HIL/HITL, scenario replay and fault injection.
Applied by platform: ISO 26262 / ISO 21448 for road vehicles · ISO 10218 for industrial robots · ISO 3691-4 for driverless industrial trucks · ISO 13482 where personal-care robot scope applies · ARP4754B / ARP4761A, DO-178C and DO-254 for certified aircraft
- Acceptance evidence
- Timestamp integrity, percentile latency, numerical correlation, scenario replay, injected faults and recovery
FPGA/ASIC-compatible LiDAR packet, trigger, capture and filter RTL, plus NumPy-to-RTL/HLS stereo vision with PCIe/AXI, host C and RISC-V/Linux integration.
04 · DSP / SDR · DEFENSE & COMMUNICATIONS
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEThree decades from modem ASICs to cloud FPGA radio
Preserve waveform behavior across platforms.
Model the signal chain first, then allocate filtering, channelization, framing and bounded AI-assisted spectrum awareness using measured transfer cost, latency, precision and SWaP.
Captured I/Q→Floating-point reference→Fixed-point envelope→Measured partition→Replay & correlation
DOMAIN TABLE STAKES
Waveform and RF closure
Implementation and transport
Sample-rate, clock, phase and frequency budgets; fixed-point error; DDC/DUC, FIR/CIC/PFB, channelizers, FFT, AGC, equalization and FEC; overflow, saturation and spectral regrowth.
RFSoC and JESD204; VITA 49 and timestamped I/Q; AXI Stream and Ethernet; GNU Radio, UHD/RFNoC, PlutoSDR, Nuand bladeRF, MATLAB/Simulink and Python/NumPy correlation.
Acceptance vocabulary: BER · EVM · ACLR · SFDR · phase noise · latency / SWaP · tailored MIL-STD-810 test methods and invoked MIL-STD-461 limits · MOSA objectives, SOSA conformance and applicable VITA/OpenVPX profile compliance scoped separately
- Acceptance evidence
- Golden-vector correlation, sustained-rate behavior, overflow coverage, BER/EVM where relevant and recorded-channel replay
Viterbi, FIR and DSL baseband at Agere/Lucent and Conexant; wireless-test FPGA/DSP at LitePoint/Teradyne; FPGA and cloud-FPGA base stations at xStellar; SDR navigation and spoof-detection prototypes at Ectron.
05 · DATACENTER & STORAGE
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEToshiba SSD SoCs and Rambus FPGA acceleration
Prove data movement under contention.
Throughput depends on descriptor ownership, credits, DMA, memory behavior, firmware and reset semantics, not only datapath width.
Host descriptors→PCIe DMA→Queue / credits→DDR / HBM→Network / storage
DOMAIN TABLE STAKES
Protocol and data-plane correctness
Storage integrity and RAS
NVMe, PCIe, CXL and Ethernet/RDMA as applicable; DMA, queues, credits, interrupts and ordering; coherency, backpressure, DDR/HBM integrity and host-driver contracts.
NAND, FTL, ECC/LDPC, bad-block handling, wear leveling, garbage collection and power-loss recovery; telemetry, fault isolation, secure boot and update/rollback.
Acceptance vocabulary: compliance and interoperability · queue-depth and tail latency · error injection · reset storms · silicon PVT characterization where in scope · storage endurance and power-loss recovery · power and soak characterization
- Acceptance evidence
- Completion integrity, sustained and tail throughput, contention, reset recovery, soak and firmware/hardware correlation
C firmware, Palladium/FPGA validation, NAND-derived tests and post-silicon bring-up for enterprise SSD controllers. A separate 16-Nios system joined PCIe Gen3, DDR3, custom accelerators and HAL/API software.
06 · SILICON & PRE-SILICON
PRINCIPAL'S PRIOR PROGRAM EXPERIENCEZeBu, HAPS and Palladium programs
Make emulation a reproducible product service.
Controlled model releases, transactors, firmware, workloads, observability, regressions and user runbooks must operate as one platform.
RTL / model release→Compile & map→Transactors→Firmware boot→Workloads & triage
DOMAIN TABLE STAKES
Model build and interfaces
Software and operations
Elaborate, synthesize, partition and map; clock/reset and memory conversion; SCE-MI/DPI transactors, speed adapters, virtual peripherals, ICE and hybrid execution; correlation among simulation, emulation and prototype.
Backdoor load, bootloader, firmware and OS boot; checkpoint and replay; workloads, assertions and waves; regression, triage, CI, utilization, versioned releases and runbooks.
Client platforms: ZeBu / HAPS · Palladium / Protium · Veloce · UVM and simulation correlation · lab and post-silicon transition
- Acceptance evidence
- Repeatable build and boot, representative workloads, regression stability, debug turnaround and demonstrated team use
An Accenture engagement supporting Meta delivered AR/VR silicon integration, transactors, automation, firmware debug and DV correlation. Microsoft work enabled Azure ML and Xbox blocks on Palladium with HBM models and DPI/backdoor loading.